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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 750 mhz, 3.8 ma 10 ns switching multiplexers ad8180/ad8182 functional block diagram 1 2 3 4 8 7 6 5 ad8180 in0 Cv s out enable select gnd in1 +v s decoder +1 +1 1 2 3 4 14 13 12 11 ad8182 Cv s out a enable a select a 5 6 7 10 9 8 select b out b enable b decoder +1 +1 decoder +1 +1 in0 a gnd in1 a +v s in1 b gnd in0 b features fully buffered inputs and outputs fast channel switching: 10 ns high speed > 750 mhz bandwidth (C3 db) 750 v/ m s slew rate fast settling time of 14 ns to 0.1% low power: 3.8 ma (ad8180), 6.8 ma (ad8182) excellent video specifications (r l 3 1 k v ) gain flatness of 0.1 db beyond 100 mhz 0.02% differential gain error 0.02 8 differential phase error low glitch: < 35 mv low all-hostile crosstalk of C80 db @ 5 mhz high off isolation of C90 db @ 5 mhz low cost fast output disable feature for connecting multiple devices applications pixel switching for picture-in-picture switching in lcd and plasma displays video switchers and routers product description the ad8180 (single) and ad8182 (dual) are high speed 2-to-1 multiplexers. they offer C3 db signal bandwidth greater than 750 mhz along with slew rate of 750 v/ m s. with better than 80 db of crosstalk and isolation, they are useful in many high speed applications. the differential gain and differential phase error of 0.02% and 0.02 , along with 0.1 db flatness beyond 100 mhz make the ad8180 and ad8182 ideal for professional video multiplexing. they offer 10 ns switching time making them an excellent choice for pixel switching (picture-in-picture) while consuming less than 3.8 ma (per 2:1 mux) on 5 v sup- ply voltages. both devices offer a high speed disable feature allowing the output to be configured into a high impedance state. this al- lows multiple outputs to be connected together for cascading stages while the off channels do not load the output bus. they operate on voltage supplies of 5 v and are offered in 8- and 14-lead plastic dip and soic packages. 500mv /div 5ns/div figure 1. ad8180/ad8182 switching characteristics table i. truth table select enable output 00 in0 10 in1 0 1 high z 1 1 high z one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
rev. b e2e ad8180/ad8182especifications ad8180a/ad8182a parameter conditions min typ max units switching characteristics channel switching time 1 channel-to-channel 50% logic to 10% output settling in0 = +1 v, in1 = e1 v; r l = 1 k w 5ns 50% logic to 90% output settling in0 = +1 v, in1 = e1 v; r l = 1 k w 10 ns 50% logic to 99.9% output settling in0 = +1 v, in1 = e1 v; r l = 1 k w 14 ns enable to channel on time 2 sel = 0 or 1 50% logic to 90% output settling in0 = +1 v, e1 v or in1 = e1 v, +1 v; r l = 1 k w 10.5 ns enable to channel off time 2 sel = 0 or 1 50% logic to 90% output settling in0 = +1 v, e1 v or in1 = e1 v, +1 v; r l = 1 k w 11 ns channel switching transient (glitch) 3 all inputs are grounded, r l = 1 k w 25 / 35 mv digital inputs logic 1 voltage sel and enable inputs 2.0 v logic 0 voltage sel and enable inputs 0.8 v logic 1 input current sel, enable = +4 v 10 200 na logic 0 input current sel, enable = +0.4 v 2 3 m a dynamic performance e3 db bandwidth (small signal) 4 ad8180r v in = 50 mv rms, r l = 5 k w 750 930 mhz e3 db bandwidth (small signal) 4 ad8182r v in = 50 mv rms, r l = 5 k w 640 780 mhz e3 db bandwidth (large signal) ad8180r v in = 1 v rms, r l = 5 k w 120 150 mhz e3 db bandwidth (large si ad8182r v in = 1 v rms, r l = 5 k w 110 135 mhz 0.1 db bandwidth 4, 5 v in = 50 mv rms, r l = 5 k w , r s = 0 w 100 mhz ad8180r v in = 50 mv rms, r l = 1 k w e5 k w , r s = 150 w 210 mhz 0.1 db bandwidth 4, 5 ad8182r v in = 50 mv rms, r l = 1 k w e5 k w , r s = 125 w 210 mhz slew rate 2 v step 750 v/ m s settling time to 0.1% 2 v step 14 ns distortion/noise performance differential gain ? = 3.58 mhz, r l = 1 k w 0.02 0.04 % differential phase ? = 3.58 mhz, r l = 1 k w 0.02 0.04 degrees all hostile crosstalk 6 ad8180r ? = 5 mhz, r l = 1 k w e80 db ? = 30 mhz, r l = 1 k w e65 db all hostile crosstalk 6 ad8182r ? = 5 mhz, r l = 1 k w e78 db ? = 30 mhz, r l = 1 k w e63 db off isolation 7 ad8180r ? = 5 mhz, r l = 30 w e89 db off isolation 7 ad8182r ? = 5 mhz, r l = 30 w e93 db voltage noise ? = 10 khze30 mhz 4.5 nv/ ? hz total harmonic distortion ? c = 10 mhz, v o = 2 v p-p, r l = 1 k w e78 dbc dc/transfer characteristics voltage gain 8 v in = 1 v, r l = 2 k w 0.982 v/v v in = 1 v, r l = 10 k w 0.986 0.993 v/v input offset voltage 112mv t min to t max 15 mv input offset voltage matching channel-to-channel 0.5 4 mv input offset drift 11 m v/ c input bias current 15 m a t min to t max 7 m a input bias current drift 12 na/ c input characteristics input resistance 1 2.2 m w input capacitance channel enabled (r package) 1.5 pf channel disabled (r package) 1.5 pf input voltage range 3.3 v output characteristics output voltage swing r l = 500 w 9 3.0 3.1 v short circuit current 30 ma output resistance enabled 27 w disabled 1 10 m w output capacitance disabled (r package) 1.7 pf power supply operating range 4 6v power supply rejection ratio +psrr +v s = +4.5 v to +5.5 v, ev s = e5 v 54 57 db power supply rejection ratio epsrr ev s = e4.5 v to e5.5 v, +v s = +5 v 45 51 db quiescent current all channels on 3.8/6.8 4.5/8 ma t min to t max 4.75/8.5 ma all channels off 1.3/2 2/3 ma t min to t max 2/3 ma ad8182, one channel on 4 ma operating temperature range e40 +85 c (@ t a = +25 8 c, v s = 6 5 v, r l = 2 k v unless otherwise noted)
notes 1 enable pin is grounded. in0 = +1 v dc, in1 = e1 v dc. select input is driven with 0 v to +5 v pulse. measure transition time from 50% of the select input value (+2.5 v) and 10% (or 90%) of the total output voltage transition from in0 channel voltage (+1 v) to in1 (e1 v), or vice versa. 2 enable pin is driven with 0 v to +5 v pulse (with 3 ns edges). state of select input determines which channel is activated (i.e., if select = logic 0, in0 is selected). set in0 = +1 v dc, in1 = e1 v dc, and measure transition time from 50% of enable pulse (+2.5 v) to 90% of the total output voltage change. in figure 5, d t off is the disable time, d t on is the enable time. 3 all inputs are grounded. select input is driven with 0 v to +5 v pulse. the outputs are monitored. speeding the edges of the se lect pulse increases the glitch magnitude due to coupling via the ground plane. removing the select input termination will lower glitch, as does increasing r l . 4 decreasing r l lowers the bandwidth slightly. increasing c l lowers the bandwidth considerably (see figure 19). 5 a resistor (r s ) placed in series with the mux inputs serves to optimize 0.1 db flatness, but is not required. increasing output capacitance w ill increase peaking and reduce band- width (see figure 20.) 6 select input which is not being driven (i.e., if select is logic 1, input activated is in1); drive all other inputs with v in = 0.707 v rms and monitor output at ? = 5 and 30 mhz. r l = 1 k w (see figure 13). 7 mux is disabled (i.e., enable = logic 1) and all inputs are driven simultaneously with v in = 0.446 v rms. output is monitored at ? = 5 and 30 mhz. r l = 30 w to simulate r on of one enabled mux within a system (see figure 14). in this mode the output impedance is very high (typ 10 m w ), and the signal couples across the package; the load imped- ance determines the crosstalk. 8 voltage gain decreases for lower values of r l . the resistive divider formed by the mux enabled output resistance (27 w ) and r l causes a gain which decreases as r l decreases (i.e., the voltage gain is approximately 0.97 v/v (3% gain error) for r l = 1 k w ). 9 larger values of r l provide wider output voltage swings, as well as better gain accuracy. see note 8. specifications subject to change without notice. ad8180/ad8182 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8180/ad8182 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. e3e rev. b absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation 2 ad8180 8-lead plastic dip (n) . . . . . . . . . . . . . . . . 1.3 watts ad8180 8-lead small outline (r) . . . . . . . . . . . . . . 0.9 watts ad8182 14-lead plastic dip (n) . . . . . . . . . . . . . . . 1.6 watts ad8182 14-lead small outline (r) . . . . . . . . . . . . . 1.0 watts input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . observe power derating curves storage temperature range n and r package . . . . . . . . . . . . . . . . . . . . . . e65 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead plastic dip package: q ja = 90 c/w; 8-lead soic package: q ja = 155 c/w; 14-lead plastic package: q ja = 75 c/w; 14-lead soic package: q ja = 120 c/w, where p d = (t j et a )/ q ja . ordering guide temperature package package model range description option ad8180an e40 c to +85 c 8-lead plastic dip n-8 ad8180ar e40 c to +85 c 8-lead soic so-8 ad8180ar-reel e40 c to +85 c 13" reel soic so-8 ad8180ar-reel7 e40 c to +85 c 7" reel soic so-8 ad8182an e40 c to +85 c 14-lead plastic dip n-14 ad8182ar e40 c to +85 c 14-lead narrow soic r-14 ad8182ar-reel e40 c to +85 c 13" reel soic r-14 ad8182ar-reel7 e40 c to +85 c 7" reel soic r-14 ad8180-eb evaluation board ad8182-eb evaluation board maximum power dissipation the maximum power that can be safely dissipated by the ad8180 and ad8182 is limited by the associated rise in junc- tion temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150 c. exceeding this limit temporarily may cause a shift in parametric perfor- mance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of +175 c for an extended period can result in device failure. while the ad8180 and ad8182 are internally short circuit protected, this may not be sufficient to guarantee that the maxi- mum junction temperature (+150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figures 2 and 3. maximum power dissipation e watts ambient temperature e 8 c 2.0 1.5 0 C50 90 C40 C30 C20 C10 0 10 20 30 50 60 70 80 40 1.0 0.5 8-lead plastic dip package 8-lead soic package t j = +150 8 c figure 2. ad8180 maximum power dissipation vs. temperature ambient temperature C 8 c 2.5 2.0 0.5 C50 90 C40 maximum power dissipation C watts C30 C20 C10 0 10 20 30 40 50 60 80 1.5 1.0 70 14-lead soic 14-lead plastic dip package t j = +150 8 c figure 3. ad8182 maximum power dissipation vs. temperature warning! esd sensitive device
e4e rev. b ad8180/ad8182etypical performance curves 500mv /div 5ns/div figure 4. channel switching characteristics dut out 250mv /div 10ns/div figure 5. enable and disable switching characteristics 50mv /div 25ns/div figure 6. channel switching transient (glitch) e7 0 e1 e2 e3 e4 e5 e6 v in = 50mv rms r l = 5k v r s = 0 v 1 normalized output C db 8180r 8182r 1m 10m 100m 1g frequency C hz figure 7. small signal frequency response C0.4 1.0 0.8 0.6 0.4 0.2 0.0 C0.2 v in = 50mv rms r l = 5k v r s = 0 v normalized flatness C db 8180r 8182r 1m 10m 100m 1g frequency C hz figure 8. gain flatness vs. frequency frequency C hz 1m 1g 10m 100m 3 0 C27 C3 C6 C9 C12 C15 C18 C21 C24 input/output level C dbv v in = 1.0v rms v in = 0.5v rms v in = 0.25v rms v in = 125mv rms v in = 62.5mv rms r l = 1k v figure 9. large signal frequency response
ad8180/ad8182 e5e rev. b frequency e hz 0.1m 1g 1m 10m 100m e10 e20 e110 e30 e40 e50 e60 e70 e80 e90 e100 crosstalk e db v in = 0.707v rms r l = 1k v ad8182r ad8180r out a out b 50 v v in 50 v 1 3 5 7 50 v ad8182 1k v 1k v figure 13. all-hostile crosstalk vs. frequency off isolation C db frequency C hz 0.03m 1g 0.1m 1m 10m 100m C10 C20 C110 C30 C40 C50 C60 C70 C80 C90 C100 all inputs = 0.446v rms r l = 30 v 8180r or 8182r enable a = logic 1 enable b = logic 0 50 v v in 50 v 8182r enable a/b = logic 1 ad8182 out a out b 30 v 30 v figure 14. off isolation vs. frequency frequency C hz 100 10 1 10 1m 100 1k 10k 100k 10m voltage noise C nv/ hz 30m figure 15. voltage noise vs. frequency 50mv /div 5ns/div figure 10. small signal transient response 500mv /div 5ns/div figure 11. large signal transient response diff gain C % 0.020 0.015 0.010 0.005 0.000 C0.005 C0.010 C0.015 C0.020 0.02 0.01 0.00 C0.01 C0.02 diff phase C degrees 1 234 567891011 ire 1 234 567891011 ire r l = 1k v ntsc figure 12. differential gain and phase error
ad8180/ad8182etypical performance curves e6e rev. b frequency e hz e25 e35 e95 100k 200m 1m 10m 100m e55 e65 e75 e85 e45 150m 2nd harmonic 3rd harmonic v out = 2v p-p r l = 1k v harmonic distortion C dbc figure 16. harmonic distortion vs. frequency disabled output and input impedance C v frequency C hz 31.6m 3.16m 31.6 1k 100m 10k 100k 1m 10m 31.6k 3.16k 316 316k 120 100 0 enabled output impedance C v 60 40 20 80 1g z out (disabled) z in (enabled) z out (enabled) figure 17. disabled output and input impedance vs. frequency psrr C db frequency C mhz 0 C20 0.03 500 0.1 1 10 100 C40 C60 C10 C30 C50 C70 +psrr Cpsrr figure 18. power supply rejection vs. frequency normalized output C db +1 0 C9 C1 C2 C3 C4 C5 C6 C7 C8 C0.4 +0.1 0 C0.1 C0.2 C0.3 normalized flatness C db v in = 500mv rms r l = 5k v c l = 0pf c l = 10pf c l = 33pf c l = 100pf c l = 100pf c l = 33pf 10m 100m 1g 4m 40m 400m frequency C hz 1m figure 19. frequency response vs. capacitive load normalized output C db +1 0 C9 C1 C2 C3 C4 C5 C6 C7 C8 C0.4 0.6 0.4 0.2 0 C0.2 normalized flatness C db v in = 50mv rms r l = 5k v r s = 0 v r s = 75 v 0.8 1.0 r s = 150 v r s = 0 v r s = 75 v r s = 150 v 10m 100m 40m frequency C hz 400m 1g 4m 1m figure 20. frequ ency response vs. input series resistance input voltage C volts 5 C1 C5 C5 5 C4C3C2C101234 4 0 C2 C4 2 1 C3 3 output voltage C volts figure 21. output voltage vs. input voltage, r l = 1 k w
ad8180/ad8182 e7e rev. b for r l > 10 k w . for heavier loads, the dc gain is approximately that of the voltage divider formed by the output impedance of the mux (typically 27 w ) and r l . high speed disable clamp circuits at the bases of q5eq8 (not shown) allow the buffers to turn off quickly and cleanly without dissipating much power once off. moreover, these clamps shunt displacement currents flowing through the junction capacitances of q1eq4 away from the bases of q5eq8 and to ac ground through low impedances. the two-pole high pass frequency response of the t switch formed by these clamps is a significant improvement over the one-pole high pass response of a simple series cmos switch. as a result, board and package parasitics, especially stray capacitance between inputs and outputs may limit the achievable crosstalk and off isolation. layout considerations: realizing the high speed performance attainable with the ad8180 and ad8182 requires careful attention to board layout and component selection. proper rf design techniques and low parasitic component selection are mandatory. wire wrap boards, prototype boards, and sockets are not recom- mended because of their high parasitic inductance and capaci- tance. instead, surface-mount components should be soldered directly to a printed circuit board (pcb). the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. the ground plane should be removed from the area near input and output pins to reduce stray capacitance. chip capacitors should be used for supply bypassing. one end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. an additional large (4.7 m fe10 m f) tantalum capacitor should be connected in parallel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies. signal traces should be as short as possible. stripline or micros- trip techniques should be used for long signal traces (longer than about 1 inch). these should be designed with a character- istic impedance of 50 w or 75 w and be properly terminated at the end using surface mount components. careful layout is imperative to minimize crosstalk. guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. input and output signal lines should fan out away from the mux as much as possible. if mul- tiple signal layers are available, a buried stripline structure hav- ing ground plane above, below, and between signal traces will have the best crosstalk performance. return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finite- impedance ground circuit that is shared between more than one input or output. minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in positioning the terminations. terminating cables directly at the connectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. moving the termination resistors close to the input pins will im- prove the frequency response, but the terminations from neigh- boring inputs should not have a common ground return. theory of operation the ad8180 and ad8182 video multiplexers are designed for fast-switching (10 ns) and wide bandwidth (> 750 mhz). this performance is attained with low power dissipation (3.8 ma per active channel) through the use of proprietary circuit techniques and a dielectrically-isolated complementary bipolar process. these devices have a fast disable function that allows the out- puts of several muxes to be wired in parallel to form a larger mux with little degradation in switching time. the low disabled output capacitance (1.7 pf) of these muxes helps to preserve the system bandwidth in larger matrices. unlike earlier cmos switches, the switched open-loop buffer architecture of the ad8180 and ad8182 provides a unidirectional signal path with minimal switch- ing glitches and constant, low input capacitance. since the input impedance of these muxes is nearly independent of the load imped- ance and the state of the mux, the frequency response of the on channels in a large switch matrix is not affected by fanout. figure 22 shows a block diagram and simplified schematic of the ad8180, which contains two switched buffers (s0 and s1) that share a common output. the decoder logic translates ttl- compatible logic inputs (select and enable ) to internal, differential ecl levels for fast, low-glitch switching. the se lect input determines which of the two buffers is enabled, unless the enable input is high, in which case both buffers are disabled and the output is switched to a high impedance state. q5 q7 q3 q1 s0 i1 i3 q6 q8 q4 q2 s1 i2 i4 decoder ad8180 1 2 3 4 in0 gnd in1 +v s 8 7 6 5 ev s out enable select figure 22. block diagram and simplified schematic of the ad8180 multiplexer each open-loop buffer is implemented as a complementary emitter follower that provides high input impedance, symmetric slew rate and load drive, and high output-to-input isolation due to its b 2 current gain. the selected buffer is biased on by fast switched current sources that allow the buffer to turn on quickly. dedicated flatness circuits, combined with the open-loop architec- ture of the ad8180 and ad8182, keep peaking low (typically < 1 db) when driving high capacitive loads, with out the need for external series resistors at the input or output. if better flatness response is desired, an input series resistance (r s ) may be used (refer to figure 20), although this will increase crosstalk. the dc gain of the ad8180 and ad8182 is almost independent of load
ad8180/ad8182 e8e rev. b applications multiplexing two rgb video sources a common video application requires two rgb sources to be multiplexed together before the selected signal is applied to a monitor. typically one source would be the pc?s normal output, the second source might be a specialized source such as mpeg video. figure 23 shows how such a circuit could be realized using the ad8180 and ad8182 and three current feedback op amps. the video inputs to the multiplexers are terminated with 75 w resistors. this has the effect of halving the signal amplitude of the applied signals. because all three multiplexers are permanen tly active, the enable pins are tied permanently low. the three select pins are tied together and this signal is used to select the source. in order to drive a 75 w back terminated load (r l = 150 w ), the multiplexer outputs are buffered using the ad8001 current feed- back op amp. a gain of two compensates for the signal halving by the ad8001 output back termination resistor so that the system has an overall gain of unity. if lower speed and crosstalk can be tolerated, either of the triple op amps, ad8013 or ad8073, can replace the three ad8001 op amps in the above circuit. because both devices have bandwidths in the 100 mhz to 140 mhz range at a gain of +2, these ampli- fiers will dominate the frequency response of the circuit. with no signal present, the total quiescent current of the cir- cuit in figure 23 is 25.6 ma (3.8 ma + 6.8 ma + 3 5 ma), or about 8.5 ma per channel. if either the ad8013 or ad8073 are used, the quiescent current will decrease to about 6.5 ma per channel. to reduce power consumption further, three ad8011 single op amps can be used. with a quiescent current of 1 ma, this will reduce the per channel quiescent current to about 4.5 ma. table ii. amplifier options for rgb multiplexer op amp comments ad8001 highest bandwidth, 440 mhz (g = +2), i sy = 5 ma ad8011 lower power consumption, bandwidth (g = +2) = 210 mhz, i sy = 1 ma ad8013 triple op amp, bandwidth (g = +2) = 140 mhz, i sy = 3.4 ma ad8073 lower power triple op amp, bandwidth (g = +2) = 100 mhz, i sy = 3.5 ma 8 7 6 5 enable enable a ev s enable b ev s +v s 0.1 m f 10 m f 0.1 m f 10 m f 0.1 m f +v s + 75 v 75 v 75 v 75 v 75 v 75 v rgb computer graphics rgb + +v s 0.1 m f 10 m f 75 v 681 v Cv s + 10 m f 0.1 m f + +v s 0.1 m f 10 m f 75 v 681 v 681 v Cv s + 10 m f 0.1 m f + +v s 0.1 m f 10 m f 75 v 681 v Cv s + 10 m f 0.1 m f select monitor 1 2 3 4 ad8180 +1 +1 1 2 3 4 14 13 12 11 ad8182 5 6 7 10 9 8 decoder +1 +1 decoder +1 +1 + + mpeg r term ad8001 681 v ad8001 681 v ad8001 r g b 0.1 m f 10 m f + 10 m f decoder figure 23. multiplexing two component video sources
ad8180/ad8182 e9e rev. b picture-in-picture or pixel switching many high end display systems require simultaneous display of two video pictures (from two different sources) on one screen. video conferencing is one such example. in this case the remote site might be displayed as the main picture with a picture of the local site inset for monitoring purposes. the circuit in fig- ure 23 could also be used to implement this picture-in-picture application. implementing a picture-in-picture algorithm is difficult for several reasons. both sources are being displayed simultaneously (i.e., during the same frame), both sources are in real time, and both must be synchronized. figure 24 shows the raster scan- ning that takes place in all monitors. during every horizontal scan that includes part of the inset, the source must be switched twice (i.e., from main to inset and from inset to main). to avoid screen artifacts, it is critical that switching is clean and fast. the ad8180 and ad8182, in the above application, switch and settle to 0.1% accuracy in 14 ns. we quadratically add this value to the 10 ns settling time of the ad8001, and get an over- all settling time of 17.2 ns. this yields a sharp, artifact-free border between the inset and the main video. inset video multiplexer must switch cleanly on each crossing main video figure 24. picture-in-picture, pixel switching color document scanner figure 25 shows a block diagram of a color document scan- ner. charge coupled devices (ccds) find widespread use in scanner applications. a monochrome ccd delivers a serial stream of voltage levels, each level being proportional to the light shining on that cell. in the case of the color image scanner shown, there are three output streams, representing red, green and blue. interlaced with the stream of voltage levels is a voltage representing the reset level (or black level) of each cell. a corre- lated double sampler (cds) subtracts these two voltages from each other in order to eliminate the relatively large offsets which are common with ccds. control and timing ad876 8/10-bit 20msps a/d ad8182 out a out b cds cds cds reference r g b c c d in0 a in1 a in1 b in0 b 100 v 4:1 mux truth table sel a, sel b ena , enb outa, outb 0 0 1 1 0 1 0 1 in0a in0b in1a in1b en a en b sel a sel b figure 25. color document scanner the next step in the data acquisition process involves digitizing the three signal streams. assuming that the analog to digital converter chosen has a fast enough sample rate, multiplexing the three streams into a single adc is generally more eco- nomic than using one adc per channel. in the example shown, we use the two 2-to-1 multiplexers in the ad8182 to create a 4-to-1 multiplexer. the enable control pins on the multiplexers allow the outputs to be wired directly together. because of its high bandwidth, the ad8182 is capable of driv- ing the switched capacitor input stage of the ad876 without additional buffering. in addition to having the required the bandwidth, it is necessary to consider the settling time of the multiplexer. in this case, the adc has a sample rate of 20 mhz which corresponds to a sam pling period of 50 ns. typically, one phase of the sampling clock is used for conversion (i.e., all levels are held steady) and the other phase is used for switch- ing and settling to the next channel. assuming a 50% duty cycle, the s ignal chain must settle within 25 ns. with a settling time to 0.1% of 14 ns, the multiplexer easily satisfies this criterion. in the example shown, the fourth (spare) channel of the ad8182 is used to measure a reference voltage. this voltage would probably be measured less frequently than the r, g and b signals. multiplexing a reference voltage offers the advantage that any temperature drift effects caused by the multiplexer will equally impact the reference voltage and the to-be- measured signals. if the fourth channel is unused, it is good design practice to tie this input to ground.
ad8180/ad8182 e10e rev. b evaluation board evaluation boards for the ad8180r and ad8182r are available which have been carefully laid out and tested to demonstrate the specified high speed performance of the devices. figure 26 and figure 27 show the schematics of the ad8180 and ad8182 evaluation boards respectively. for ordering information, please refer to the ordering guide. because the footprint of the ad8180 fits directly on to that of the ad8182, one board layout can be used for both devices. in the case of the ad 8180, only the top half of the board is populated. figure 28 shows the silkscreen of the component side and fig- ure 30 shows the silkscreen of the solder side. figures 29 and 31 show the layout of the component side and solder side respectively. the evaluation board is provided with 49.9 w termination resis- tors on all inputs. this is to allow the performance to be evalu- ated at very high frequencies where 50 w termination is most popular. to use the evaluation board in video applications, the termination resistors should be replaced with 75 w resistors. the multiplexer outputs are loaded with 4.99 k w resistors. in order to avoid large gain errors, these load resistors should be greater than or equal to 1 k w . for connection to external instru- ments, oscilloscope scope probe adapters are provided. this allows direct connection of fet probes to the board. for verifi- cation of data sheet specifications, use of fet probes with a bandwidth > 1 ghz is recommended because of their low input capacitance. the probe adapters used on the board have the same footprint as sma, smb and smc type connectors allow- ing easy replacement if necessary. 8 7 6 5 +v s c4 10 m f c1 0.1 m f r10 49.9 v 1 2 3 4 ad8180r decoder +1 +1 + r1 49.9 v in1 in0 select r9 49.9 v enable r8 49.9 v + Cv s c3 10 m f c2 0.1 m f r7 4.99k v out (scope probe adapter) unless otherwise noted, connectors are sma type figure 26. ad8180r evaluation board Cv s + +v s c1 0.1 m f c4 10 m f r10 49.9 v 1 2 3 4 14 13 12 11 ad8182r 5 6 7 10 9 8 decoder +1 +1 decoder +1 +1 r1 49.9 v in1 a in0 a r9 49.9 v select a r8 49.9 v enable a r2 49.9 v in1 b in0 b r3 49.9 v r4 49.9 v select b r5 49.9 v enable b + c3 10 m f c2 0.1 m f outb (scope probe adapter) outa (scope probe adapter) r6 4.99k v r7 4.99k v unless otherwise noted, connectors are sma type figure 27. ad8182r evaluation board
ad8180/ad8182 e11e rev. b c1 analog devices ad8180/82 evaluation board j1 in0a j10 sel a j2 in1a j3 in1b in0b j4 j9 j8 en a r10 r1 u1 r2 r3 v+ vC sel b j5 j6 en b a b c2 r5 j7 r9 r 8 r4 figure 28. component side silkscreen figure 29. board layout (component side) c3 c4 r7 r 6 figure 30. solder side silkscreen figure 31. board layout (solder side) notes 1. ad8180r/ad8182r evaluation board inputs are configured with 50 w impedance striplines. this fr4 board type has the following stripline dimensions: 60-mil width, 12-mil gap between center conductor and outside ground plane is- lands, and 62-mil board thickness. 2. several types of sma connectors can be mounted on this board: the side-mount type, which can be easily installed at the edges of the board, and the top-mount type, which is placed on top. when using the top-mount sma connector, it is recommended that the stripline on the outside 1/8" of the board edge be removed with an x-acto blade as this unused stripline acts as an open stub, which could degrade the small- signal frequency response of the mux. 3. input termination resistor placement on the evaluation board is critical to reducing crosstalk. each termination resistor is oriented so that ground return currents flow counterclock- wise to a ground plane island. although the direction of this ground current flow is arbitrary, it is important that no two input or output termination resistors share a connection to the same ground island.
ad8180/ad8182 e12e rev. b c2182ae0e1/00 (rev. b) printed in u.s.a. e12e outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead plastic soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19)

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